Semiconductor nano-rod devices

ABSTRACT

In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

This application is a divisional of patent application Ser. No.10/370,792, entitled “Semiconductor Nano-Rod Devices,” filed on Feb. 20,2003, which application is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to methods for manufacturingsemiconductor devices. In one aspect, the present invention relates to amethod of forming a nano-rod structure for a channel of a field effecttransistor.

BACKGROUND

Metal-oxide-semiconductor field effect transistor (MOSFET) technology iscurrently the dominant semiconductor technology used for manufacturingultra-large scale integrated (ULSI) circuits. As the gate length of theMOSFET is scaled down into the sub-30 nm regime for improved performanceand density, the source and drain increasingly interact with the channelto sometimes gain influence on the channel potential. Hence, atransistor with a short gate length often suffers from problems relatedto the inability of the gate to substantially control the on/off statesof the channel, which is often called short-channel effects.

Increased body doping concentration, reduced gate oxide thickness, andjunction depths are some ways to suppress short-channel effects.However, for device scaling well into the sub-30 nm regime, therequirements for body-doping concentration, gate oxide thickness, andsource/drain doping profiles become increasingly difficult to meet usingconventional device structures based on bulk silicon substrates. Thus,alternative device structures that offer better control of short-channeleffects are being considered to enable the continued scaling down oftransistor sizes.

A highly scalable device structure that offers superior control ofshort-channel effects is a wrap-around gate structure for a transistor(a.k.a., surround-gate or gate-all-around transistor structure). Awrap-around gate structure typically has a gate that surrounds or wrapsaround a channel region. This structure effectively improves thecapacitance coupling between the gate and the channel, as compared toconventional bulk silicon substrate transistor structures, double-gatetransistor structures, and triple-gate transistor structures. With thewrap-around gate structure, the gate gains significant influence on thechannel potential, and therefore improves suppression of short-channeleffects. A wrap-around gate structure typically allows the gate lengthto be scaled down by about 50% more compared to a double-gate structure.

There are several different ways to implement a wrap-around gatetransistor structure. For example, the transistor channel may beoriented vertically or horizontally. Many of the existing designs forhorizontally oriented channels have a square or rectangular shapedcross-section. When the channel cross-section is rectangular or square,enhanced field effect at the corners of the rectangle may cause thatpart of the transistor to turn on earlier (i.e., having a lowerthreshold voltage) than parts of the transistor at the flat sides of therectangular channel cross-section. This may result in a parasiticoff-state leakage. Hence, a cylindrical channel cross-section ispreferred over a rectangular channel cross-section.

Current attempts at obtaining a more circular channel cross-section aremade by oxidizing the silicon beam forming the channel to round thecorners of the rectangular channel cross-section. However, this methodrequires a large amount of oxidation, and hence a large amount of oxideformation, to convert the rectangular channel cross-section shape to arounded or circular channel cross-section. Hence, there is a need for away to manufacture a transistor channel having a rounded or circularcross-section shape without having to form excessive oxide about thechannel.

SUMMARY

The problems and needs outlined above are addressed by embodiments ofthe present invention. In accordance with one aspect of the presentinvention, a method of manufacturing a semiconductor device is provided.This method includes the following steps. A semiconductor layer ispatterned to form a source region, a channel region, and a drain regionin the semiconductor layer. The channel region extends between thesource region and the drain region. Corners of the channel region arerounded by annealing the channel region.

Next, some example annealing parameters that may be used are described.The annealing may occur in a reaction chamber having an environmenttherein including a gas of hydrogen, nitrogen, a mixed gas includinghydrogen and argon, a mixed gas including hydrogen and nitrogen, or aninert gas. The annealing environment may be H₂ gas at a pressure rangingfrom about 1.0×10⁻⁹ torr to about 800 torr. The annealing environmentmay be N₂ gas at a pressure ranging from about 1.0×10⁻⁹ torr to about800 torr. The annealing may occur in a reaction chamber having anevacuated environment. The annealing environment may be a vacuumenvironment at a pressure ranging from about 1.0×10⁻¹⁰ torr to about1.0×10 ⁻³ torr. The annealing may occur in a reaction chamber having atemperature ranging from about 600° C. to about 1200° C. therein. Theannealing occurs at an anneal time ranging from about 1 second to about2 hours. The annealing may be performed in a hydrogen gas (H₂)environment at about 900° C. for about 2 minutes.

In accordance with another aspect of the present invention, a method ofmanufacturing a semiconductor device is provided. This method includesthe following steps. A semiconductor layer is patterned to form a sourceregion, a channel region, and a drain region in the semiconductor layer.The channel region extends between the source region and the drainregion. Corners of the channel region are rounded by annealing thechannel region. The insulating layer is etched using an etch chemistryselective against etching the semiconductor layer. The etching isperformed long enough so that at least a segment of the rounded channelregion is suspended above a proximate portion of the insulating layer. Agate dielectric material is formed on a surface of and about the roundedchannel region. A gate electrode material is formed on the gatedielectric and about the rounded channel region. The gate electrodematerial is patterned to form a gate electrode. The gate electrodeincludes a gate wrap region that wraps around the rounded channel regionand a gate contact region extending therefrom.

In accordance with yet another aspect of the present invention, asemiconductor device is provided, which includes an insulating layer, anunderlying layer, a layer of semiconductor material, a gate dielectric,and a gate electrode. The insulating layer is over the underlying layer.The layer of semiconductor material is over the insulating layer. Thesemiconductor layer has a source region, a drain region, and an annealednano-rod structure extending between the source and drain regions. Thegate dielectric is formed on the surface of at least a segment of thenano-rod structure. The gate electrode is formed on the surface of thegate dielectric at the segment. Preferably, the gate dielectric and thegate electrode are both formed completely around the nano-rod structureat the segment. Preferably, the nano-rod structure has a cross-sectiondiameter less than about 65 nm.

In accordance with still another aspect of the present invention, asemiconductor device including a plurality of transistors, is provided.Each of the plurality of transistors includes an annealed semiconductorlayer, a gate dielectric surface layer, and a gate electrode. Theannealed semiconductor layer has a source region, a drain region, and achannel region formed therein. The channel region extends between thesource region and the drain region. The source region has asubstantially flat source contact portion. The drain region has asubstantially flat drain contact portion. The channel region has asubstantially circular cross-section shape. The gate dielectric surfacelayer wraps around a segment of the channel region. The gate electrodehas a gate wrap region that wraps around the segment of the channelregion and a gate contact region extending therefrom. The gatedielectric layer is between the segment of the channel region and thegate wrap region of the gate electrode.

BRIEF DESCRIPTION

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIGS. 1A, 2A, 3A, 4A, 5A, and 6A show simplified perspective views ofone transistor device being manufactured on a semiconductor device inaccordance with a preferred embodiment of the present invention;

FIGS. 1B, 2B, 3B, 4B, 5B, and 6B are simplified cross-section views ofFIGS. 1A, 2A, 3A, 4A, 5A, and 6A, respectively, as taken along lines1B-1B, 2B-2B, 3B-3B, 4B-4B, 5B-5B, and 6B-6B, respectively; and

FIGS. 7A-7D show some possible variations of the nano-rod structureformed after an annealing processing in accordance with the presentinvention.

DETAILED DESCRIPTION

The use of presently preferred embodiments are discussed in detailbelow. It should be appreciated, however, that the present inventionprovides many applicable inventive concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative of specific ways to make and use the invention,and do not limit the scope of the invention.

Example embodiments of the present invention will be described herein ina specific context of making semiconductor devices, such as transistors.In other embodiments not shown, embodiments of the present inventionalso may include nano-wires or quantum-wires formed in accordance withthe present invention. The present invention may also be applied,however, to other situations.

A preferred manufacturing process in accordance with the presentinvention may be used to make a transistor device. Some of themanufacturing steps of this preferred embodiment being used to make atransistor embodiment are illustrated in FIGS. 1A-6B. While describingthe structure formation steps shown in FIGS. 1A-6B, process parametersand steps for the preferred embodiment will described, as well as someof the possible alternatives or variations of the process parameters andsteps. However, the process parameters shown and/or described herein aremerely examples to illustrate and describe the present invention. Withthe benefit of this disclosure, one of ordinary skill in the art willlikely realize other variations and embodiments of the present inventionwithin the scope and spirit of the appended patent claims.

FIGS. 1A, 2A, 3A, 4A, 5A, and 6A show simplified perspective views ofone transistor device 20 being manufactured on a semiconductor device.Such a semiconductor device will often have millions of thesetransistors 20. However, for purposes of illustration and discussion,only one transistor device 20 is shown and the remainder of thesemiconductor device is not shown. FIGS. 1B, 2B, 3B, 4B, 5B, and 6B aresimplified cross-section views of FIGS. 1A, 2A, 3A, 4A, 5A, and 6A,respectively, as taken along lines 1B-1B, 2B-2B, 3B-3B, 4B-4B, 5B-5B,and 6B-6B, respectively.

Referring to FIGS. 1A and 1B, an intermediate structure is shown havingan insulating layer 22 formed on an underlying layer 24. A semiconductorlayer 26 is formed on the insulating layer 22. This type of structure issometimes referred to as a silicon-on-insulator substrate and iscommonly available as a starting material. A patterned active regionmask 28 is formed on the semiconductor layer 26. The mask 28 may beformed from a pad silicon oxide layer 30 and a silicon nitride layer 32,for example. With the mask 28 in place having a pattern desired to beformed in the semiconductor layer 26, the semiconductor layer 26 ispreferably anisotropically etched (e.g., dry plasma etching) to conformthe semiconductor layer 26 to the pattern of the mask 28.

The underlying layer 24 will often be a silicon wafer, for example.However, the underlying layer 24 may be another type of layer, includingbut not limited to: an elemental semiconductor, such as germanium; analloy semiconductor, such as silicon-germanium; or a compoundsemiconductor, such as gallium arsenide or indium phosphide, forexample.

The insulating layer 22 in some embodiments may be referred to as a“buried oxide” layer. However, the insulating layer 22 may be composedof a material or a combination of materials from a large variety ofmaterials, including but not limited to: silicon dioxide, siliconnitride, aluminum oxide, plastic, or polymer, for example. In acurrently preferred embodiment, the insulating layer 22 is composed ofsilicon dioxide (SiO₂).

The semiconductor layer 26 may be composed of a material or acombination of materials from a large variety of materials, includingbut not limited to: any semiconductor material, silicon, carbon,elemental semiconductor material (e.g., germanium), alloy semiconductormaterial (e.g., silicon-germanium, silicon-germanium-carbon), compoundsemiconductor material (e.g., indium phosphide, gallium arsenide),plastic, or polymer, for example. Such materials may be in crystallineor amorphous forms. In a currently preferred embodiment, thesemiconductor layer 26 is composed of silicon. Hence, in the preferredembodiment shown in FIGS. 1A-6B, the semiconductor layer 26 is a siliconlayer.

In FIGS. 2A and 2B the mask 28 has been removed and the patternedsemiconductor layer 26 remains in the form of an H-shaped, thin siliconisland. However, in other embodiments (not shown), the patternedsemiconductor layer 26 may have other shapes (e.g., U-shaped, V-shaped,I-shaped, L-shaped, etc.). The thickness of the patterned silicon layeror island 26 may range from about two angstroms to about 1000 angstroms,for example. The patterned silicon layer 26 has a source region 40, adrain region 42, and a channel region 44. The channel region 44 extendsbetween the source region 40 and the drain region 42. As shown in FIG.2A, the channel region 44 has a width that is much narrower than thecontact pad portions 50 and 52 of the source and drain regions 40 and42, respectively.

Next, the silicon atoms in the patterned silicon layer 26 arere-arranged by annealing the silicon layer 26 at elevated temperatures.The re-arrangement is induced by surface migration of silicon atomsdriven by a tendency to minimize surface tension. During the annealing,the re-arrangement of the atoms at the narrow channel region 44 causesthe corners of the channel region 44 to be rounded, as shown in FIGS. 3Aand 3B, to transform the channel region 44 into a nano-rod structure 60.If carried out long enough and/or under sufficient heat, the resultingnano-rod structure 60 may be completely rounded having a circular-shapedcross-section, as shown in FIG. 3B. The contact pad portions 50 and 52of the source and drain regions 40 and 42 will also likely experienceslight shape changes, such as rounding of at least some of theircorners. But because the contact pad portions 50 and 52 are much widerthan the channel region, these contact pad portions 50 and 52 willtypically still be substantially flat in shape or with only a slightcurvature. The contact pad portions of the source and drain regionsserve to provide a portion onto which metallic or conductive materialsform electrical connection with the source and drain regions. It isunderstood that the contact pad is an optional feature of thisinvention. If the contact pad portions of the source and drain regionsare omitted, the patterned semiconductor layer may be I-shaped, forexample. In this case, the electrical connection between the metallic orconductive material and the source and drain regions may be formeddirectly on the nano-rod structure.

Example parameters for the annealing process used to round the cornersof the channel region 44 will be described next. The temperature for theannealing process may range from about 600° C. to about 1200° C. Theanneal time may range from about 1 second to about 2 hours. The pressurein the reaction chamber (not shown) used for the annealing process mayvary, depending in part upon the environment within the reactionchamber. The reaction chamber may be a chemical vapor deposition (CVD)epitaxial reactor, for example. The annealing process may occur in areaction chamber having an environment of hydrogen gas (H₂) at a partialpressure ranging from about 1.0×10 ⁻⁹ torr to about 800 torr. In anotherembodiment, the annealing environment may be evacuated (i.e., a vacuumenvironment) at a pressure ranging from about 1.0×10⁻¹⁰ torr to about1.0×10⁻³ torr. In still another embodiment, the annealing environmentmay be nitrogen gas (N₂) at a pressure ranging from about 1.0×10⁻⁹ torrto about 800 torr. The annealing environment may also be one of thefollowing environments (but not limited to): an environment of a mixedgas including hydrogen and argon; an environment of a mixed gasincluding hydrogen and nitrogen; an environment with other gases inaddition to hydrogen to form a mixed gas ambient; or an environment ofan inert gas, for example.

In a preferred embodiment, the annealing process is performed in ahydrogen gas (H₂) ambient at about 900° C. for about 2 minutes. Duringtesting, annealing a 28 nm thick silicon channel region 44 under suchconditions did not reveal crystal defects.

After forming the nano-rod structure 60, the insulating layer 22 may beetched to expose the bottom surface of the nano-rod 60, as shown inFIGS. 4A and 4B. The nano-rod 60 is supported by the contact portions 50and 52 of the source and drain regions 40 and 42. It is preferred toetch away the insulating layer 22 beneath the nano-rod 60 at leastenough to allow the gate to wrap around the nano-rod 60 for optimum gatecontrol performance. The use of the annealing process of the presentinvention to form a nano-rod structure 60 (described above) may also beapplied to a non-wrap-around gate design (i.e., where the gate electrodeonly covers three sides of the gate channel, or where the gate electrodedoes not completely wrap around the gate channel).

Next, a gate dielectric material 62 is formed on the surface of andabout the nano-rod structure 60 (as well as on the other exposedportions of the silicon layer 26), as shown in FIGS. 5A and 5B. As shownin FIG. 5B, because the nano-rod 60 is exposed on all sides afteretching away part of the insulting layer 22, the gate dielectricmaterial 62 may be formed completely around the nano-rod surface. Thegate dielectric material 62 may be an oxide formed by thermal oxidationor atomic-layer CVD for uniform deposition, for example. Hence, the gatedielectric will likely form on all exposed areas, including the contactportions 50, 52 of the source and drain regions 40, 42. The gatedielectric material may take the form of a variety of compositions,including but not limited to: silicon dioxide (SiO₂), silicon oxynitride(SiO_(x)N_(y)), HfO₂, ZrO₂, Al₂O₃, La₂O₃, or other high permittivitymaterials, for example.

A gate electrode material is then deposited, masked, and etched to formthe gate electrode 64, as shown in FIGS. 6A and 6B. The gate electrodematerial may be selected from a variety of materials, including but notlimited to: a semiconductor material (e.g., poly-silicon,poly-silicon-germanium); a metal material (e.g., molybdenum, tungsten,titanium); a metallic nitride (e.g., tantalum nitride, titaniumnitride); or any combination thereof, for example. As shown in FIG. 6B,because the nano-rod 60 is elevated above the insulating layer 22 (atleast where the channel will be formed), the gate electrode 64 may beformed completely around the nano-rod 60, as preferred. During or afterthe etching of the gate electrode material to form the patterned gateelectrode 64, the gate dielectric material 62 may be removed from thesource and drain regions, as shown in FIG. 6A.

Because the gate dielectric 62 is preferably aligned with the gateelectrode 64 at the channel, the gate dielectric 62 can be self-alignedwith the gate electrode 64 by simply etching the gate electrode materialwith an etch chemistry that will also etch away the gate dielectricmaterial 62 while being selective against etching the silicon layer 26.Also, because the gate dielectric 62 at the gate channel is shielded bythe gate electrode 64, the ion implantation processes for doping thesilicon layer 26 outside of the channel (i.e., to form the source anddrain of the transistor 20) may be self-aligning as well.

As shown in FIGS. 7A, 7B, 7C, and 7D, the resulting shape of thenano-rod 60 formed at the channel region 44 may vary, depending on theannealing parameters used. For example, the nano-rod portion 60 shown inFIG. 7A has a generally rectangular shaped cross-section with roundedcorners (i.e., more than 4 crystal faces). The nano-rod portion 60 shownin FIG. 7B has a generally oval-shaped cross-section. In otherembodiments, the nano-rod cross-section may have a rounded butarbitrarily shaped or somewhat arbitrarily shaped, as shown in FIG. 7Cfor example. However, as described above, the preferred shape of thenano-rod cross-section for a preferred transistor embodiment iscircular, as shown in FIG. 7D. Preferably, the nano-rod 60 has adiameter no larger than about 65 nm. The diameter of the nano-rodcross-section may be in the order of nanometers (e.g., about 4 nm), andsuch nano-rods may be used for the channel of a field-effect transistor,for example.

In another manufacturing embodiment (not shown) of present invention,after FIG. 2A, part of the insulating layer 22 may be etched away beforethe annealing process for rounding the corners of the channel region 44.Also, after FIG. 5A, the gate dielectric material 62 may be patternedand etched (to leave a gate dielectric portion around the nano-rod 60where the gate channel will be formed) before the deposition of the gateelectrode material. In still another embodiment, after FIG. 5A, the gateelectrode material may be etched using a first etch chemistry to formthe gate electrode 64, and then the gate dielectric material 62 may beetched using a second etch chemistry after forming the gate electrode64. In such case, the gate electrode 64 may act as a self-aligning maskfor the etching of the gate dielectric material 62 to shield the gatedielectric between the gate electrode 64 and the nano-rod 60.

Although several embodiments of the present invention have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the processes, machines,manufactures, compositions of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufactures, compositions of matter, means, methods, orsteps, presently existing or later to be developed, that performsubstantially the same function and/or achieve substantially the sameresult as the corresponding embodiments described herein may be utilizedaccording to the present invention. Accordingly, the appended claims areintended to include within their scope such processes, machines,manufactures, compositions of matter, means, methods, or steps.

1. A semiconductor device comprising: an insulating layer over anunderlying layer; a layer of semiconductor material over the insulatinglayer, the semiconductor layer having a source region, a drain region,and an annealed nano-rod structure extending between the source anddrain regions; a gate dielectric formed on the surface of at least asegment of the nano-rod structure; and a gate electrode formed on thesurface of the gate dielectric at the segment.
 2. The semiconductordevice of claim 1, wherein the gate dielectric is formed completelyaround the nano-rod structure at the segment.
 3. The semiconductordevice of claim 2, wherein the gate electrode is formed completelyaround the nano-rod structure at the segment.
 4. The semiconductordevice of claim 1, wherein the semiconductor material is selected from agroup consisting of silicon, germanium, silicon-germanium alloy,silicon-germanium-carbon alloy, indium phosphide compound, and galliumarsenide compound.
 5. The semiconductor device of claim 1, wherein theinsulating layer comprises a material selected from a group consistingof silicon dioxide, silicon nitride, and aluminum oxide.
 6. Thesemiconductor device of claim 1, wherein the underlying layer is asilicon substrate.
 7. The semiconductor device of claim 1, wherein thegate dielectric comprises a material selected from a group consisting ofsilicon dioxide, silicon oxynitride, HfO2, ZrO2, Al2O3, and La2O3. 8.The semiconductor device of claim 1, wherein the gate electrodecomprises a material selected from a group consisting of asemiconducting material, a metal, and a metal nitride.
 9. Thesemiconductor device of claim 1, wherein the nano-rod structure has across-section diameter less than about 65 nm.
 10. The semiconductordevice of claim 1, wherein the nano-rod structure has a substantiallycircular cross-section.
 11. The semiconductor device of claim 1, whereinthe nano-rod structure has rounded corners.
 12. A semiconductor devicecomprising a plurality of transistors, wherein each of the plurality oftransistors comprises: an annealed semiconductor layer having a sourceregion, a drain region, and a channel region formed therein, the channelregion extending between the source region and the drain region, thechannel region comprising a nano-rod structure with rounded corners; agate dielectric formed on the surface of at least a segment of thenano-rod structure; and a gate electrode formed on the surface of thegate dielectric at the segment, the gate electrode having a gate contactregion extending therefrom.
 13. The semiconductor device of claim 12,wherein the gate dielectric is formed completely around the nano-rodstructure at the segment.
 14. The semiconductor device of claim 13,wherein the gate electrode is formed completely around the nano-rodstructure at the segment.
 15. The semiconductor device of claim 12,wherein the semiconductor material is selected from a group consistingof silicon, germanium, silicon-germanium alloy, silicon-germanium-carbonalloy, indium phosphide compound, and gallium arsenide compound.
 16. Thesemiconductor device of claim 12, further comprising an insulating layerover an underlying layer, wherein the semiconductor layer is formed overthe insulating layer.
 17. The semiconductor device of claim 16, whereinthe insulating layer comprises a material selected from a groupconsisting of silicon dioxide, silicon nitride, and aluminum oxide, andwherein the underlying layer is a silicon substrate.
 18. Thesemiconductor device of claim 12, wherein the gate dielectric comprisesa material selected from a group consisting of silicon dioxide, siliconoxynitride, HfO2, ZrO2, Al2O3, and La2O3, and wherein the gate electrodecomprises a material selected from a group consisting of asemiconducting material, a metal, and a metal nitride.
 19. Thesemiconductor device of claim 12, wherein the nano-rod structure has across-section diameter less than about 65 nm.
 20. A semiconductor devicecomprising a plurality of transistors, wherein each of the plurality oftransistors comprises: an annealed semiconductor layer having a sourceregion, a drain region, and a channel region formed therein, the channelregion extending between the source region and the drain region, thechannel region having a substantially circular cross-section shape, agate dielectric layer around a segment of the channel region, and a gateelectrode having a gate wrap region that wraps around the segment of thechannel region and a gate contact region extending therefrom, whereinthe gate dielectric layer is between the segment of the channel regionand the gate wrap region of the gate electrode.